Microsupercomputers : Design and Implementation Stanford University Computer Systems Laboratory Technical Progress Report

This paper introduces a two-port BiCMOS static mem-ory cell that combines ECL level word-line voltage swings andemitter-follower bit line coupling with a static CMOS latchto achieve access times comparable to those of high-speedbipolar SRAM's, while preserving the high density and lowpower of CMOS memory arrays. The memory can be ac-cessed for read and write independently and simultaneously,making it especially attractive for the design of video, cacheand other application-specific memories. An experimental4Kxlbit two-port memory integrated in a 1.5/jm-5GHz BiC-MOS technology exhibits a read access time of 4 nsec and apower dissipation of 550 mW.